Analog-to-digital converters (ADCs) are commonly found in communications systems and audio, video and multimedia electronics systems. One type of ADC, shown in FIG. 1, is the delta-sigma ADC 10. The delta-sigma ADC 10 consists of a sample and hold (S/H) circuit 11, a subtractor 12, a discrete-time integrator 14, a quantizer 16, a one-bit digital-to-analog converter (DAC) 18 in a feedback loop 20, and a digital decimation filter 22. The delta-sigma ADC 10 operates as follows. An analog input signal is received by the S/H circuit 11, which provides a sampled analog input signal to the subtractor 12. The subtractor 12 subtracts an estimate signal provided by the DAC 18 from the sampled analog input signal, generating an error signal that is input to the integrator 14. As explained in more detail below, the integrator 14 behaves as a filter. The quantizer 16 samples the analog signal received from the integrator 14 and provides a stream of digital output samples. The one-bit DAC 18 converts the digital samples from the quantizer 16 into an analog estimate signal, which is fed to the subtractor 12, via the feedback loop 20. The digital decimation filter 22 reduces the data rate down from the oversampling sampling rate so that the data is more manageable, and filters the digital output samples to remove quantization noise.
The delta-sigma converter 10 employs techniques known as “oversampling” and “noise shaping” to increase the signal-to-noise ratio (SNR) in the signal band of interest. Oversampling spreads the quantization noise power, produced by the quantizer 16 during conversion, over a bandwidth equal to the sampling frequency, which is at a frequency much greater than the signal bandwidth. Noise shaping is performed by the integrator 14, which behaves, in conjunction with the loop, as an all-pass filter on the signal, and as a highpass filter on the noise created by the quantizer during conversion. The effect of noise shaping is a redistribution of the quantization noise such that most of the noise energy is shifted to a frequency band that is outside the signal bandwidth.
One well-known improvement of the delta-sigma ADC is the Multi-StAge NoiSe SHaping (MASH) delta-sigma ADC. According to this improvement, quantization noise is reduced by increasing the order of the noise-shaping transfer function through the use of multiple modulator stages connected together in a semi-cascade type of arrangement. FIG. 2 shows a block diagram of a typical MASH delta-sigma ADC 20. MASH delta-sigma ADC 20 is composed of analog 22 and digital 24 sections. The analog section 22 includes two or more modulators 23-1, 23-2, . . . ,23-N. Modulator 23-1 contains a sample and hold (S/H) circuit 26, one or more series integrators 28, a quantizer 30, and a DAC 32 disposed in a feedback loop 34. The order of a modulator is determined by the number of series integrators in the noise shaping path. A zero order modulator is composed of only a single quantizer. A MASH delta-sigma ADC can theoretically contain an arbitrary number of modulators or stages, although two or three is common. The MASH architecture is desirable because it offers superior high order noise shaping with guaranteed stability. The benefit is a less complex hardware implementation because a lower oversampling ratio (OSR) is permissible, and consequently a lower sampling rate is required to achieve the same SNR as compared to the basic delta-sigma ADC shown in FIG. 1.
The concept of noise cancellation in a MASH architecture is illustrated in FIG. 3, which shows a block diagram of a two-stage MASH ADC 30 where the second modulator 34 is zero order. In the frequency domain, the signal input is represented by X, the quantization noise from a first modulator 32 is Q1 and from quantizer 34 is Q2 NTF1 represents the analog Noise Transfer Function (NTF) filter from the modulator 32, NTF1,est represents the NTF of digital filter 36, and Nd1 represents a noise component due to other sources in the first modulator 32. The digital filter 36 is designed to match the analog NTF so that the effect of the first modulator 32 quantization error (Q1) is canceled at the output. If the analog and digital filters do not match (i.e., NTF1−NTF1,est is not zero over all frequencies) the SNR performance is degraded. Hence, one disadvantage of the MASH architecture is that it is sensitive to matching accuracy of analog and digital processing circuits.
FIGS. 4A and 4B show examples of switched-capacitor implementations of a two-phased S/H circuit 40 and a band-pass integrator 42, respectively, which may be used in a MASH delta-sigma ADC like the one shown in FIG. 2. The two-phased S/H circuit 40 allows more time to complete the capture of signals than a single-phased sampling element. While one capacitor is sampling the input the other is delivering its charge to the selected integrator feedback capacitor. This sequence eases the speed requirements on the Operational Transconductance Amplifier (OTA). FIG. 4C shows a timing diagram for the two-phased S/H circuit 40 in FIG. 4A: switches are closed when the corresponding waveform is high. The integrator in FIG. 4B provides a band-pass NTF when used in the modulator shown in FIG. 3. Whereas a single-ended configuration is shown, differential configurations can also be used. FIG. 4D shows a timing diagram for the band-pass integrator 42 in FIG. 4B.
Non-ideal switches, capacitors, and OTAs, etc., in the S/H circuit 40, the integrator 42, and other analog circuitry of the modulator, increase noise and introduce in-band spurious signals. The noise and spurious signals operate to reduce the SNR performance of the ADC. Various attempts to overcome this matching problem in MASH architectures have been proposed. A first approach is to simply provide for more accurate matching of analog components. However, this approach is unattractive because accurate matching of circuits implies larger devices, slower speed, higher power, and extensive design effort to achieve the required analog tolerances.
A second approach, described in U.S. Pat. No. 6,075,820, utilizes the injection of a signal at the input to the delta-sigma ADC. A drawback of this technique, however, is that the ADC input must be disconnected from its nominal input to perform this calibration.
A third approach is to provide digital compensation using a test signal injected at the quantizer input and a single adaptive filter. This technique is described by P. Kiss, et al., in “Adaptive Digital Correction of Analog Errors in MASH ADC's—Part II: Correction Using Test-Signal Injection,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 7, July 2000, pp. 629-638. A block diagram of such a MASH ADC 50 is shown in FIG. 5. The MASH ADC 50 includes a first modulator 51 and an adaptive digital filter 52, which is augmented by a fixed filter 53. A test signal 54 is summed with the quantization noise from the first modulator 51 and also applied to a coefficient generator 55 where it is correlated with the ADC final output Y. The coefficient generator 55 correlates the test signal 54 with the ADC final output Y, deriving coefficients, which it provides to an adaptive compensation filter 56 (i.e. a finite impulse response (FIR) filter). The output Y3 from a second modulator 57 is filtered by the FIR filter 56 and the fixed filter 53. The outputs of adaptive filter 52 and fixed filter 53 are summed by a first summer 58, to form a composite digital NTF filter. The digital NTF filter is modified in this way to track uncertainty in the analog NTF. Finally, the composite digital NTF filter output is summed with the delayed output of the first modulator 51 by a second summer 59.
So long as the adaptation update rate is fast enough, fixed or slowly time varying changes in the analog NTF can be tracked out by the technique employed by MASH ADC 50 in FIG. 5. However, analog variations that occur at rates commensurate with the clock frequency cannot be tracked by this technique. This can be explained as follows. The digital NTF filter is based on minimizing the residual test signal over digital samples at the ADC output Y. In order to correct analog variations, correlations using multiple digital samples must be made to derive the proper coefficients of the digital NTF filter, thereby delaying the correction and limiting the speed at which the digital NTF filter tracks the analog NTF to a fraction of the sample rate. Consequently, a drawback of the approach shown in FIG. 5 is that it is limited in its ability to compensate for analog NTF characteristics that are time variant at the clock frequency.